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Verification by Error Modeling
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Verification by Error Modeling

Although there are no widely adhered standards for a design flow, most companies have their own established practices, which they follow closely for in-house design processes. In practice, initial phases of preparing a design specification are susceptible to potential errors, as it is very difficult to grasp all the details in a complex design.
Alaotsikko
Using Testing Techniques in Hardware Verification
Painos
2003 ed.
ISBN
9781402076527
Kieli
englanti
Paino
446 grammaa
Julkaisupäivä
30.11.2003
Sivumäärä
216