Tallenna
Switch-Level Timing Simulation of MOS VLSI Circuits
Kirjailija:
nidottu, 2011
englanti
Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging.
- Kirjailija
- Vasant B. Rao, David V. Overhauser, Timothy N. Trick, Ibrahim N. Hajj
- Painos
- Softcover reprint of the original 1st ed. 1989
- ISBN
- 9781461289630
- Kieli
- englanti
- Paino
- 310 grammaa
- Julkaisupäivä
- 5.10.2011
- Kustantaja
- Springer-Verlag New York Inc.
- Sivumäärä
- 210
