Tallenna
Switch-Level Timing Simulation of MOS VLSI Circuits
Kirjailija:
sidottu, 1988
englanti
Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging.
- Kirjailija
- Vasant B. Rao, David V. Overhauser, Timothy N. Trick, Ibrahim N. Hajj
- Painos
- 1989 ed.
- ISBN
- 9780898383027
- Kieli
- englanti
- Paino
- 446 grammaa
- Julkaisupäivä
- 30.11.1988
- Kustantaja
- Kluwer Academic Publishers
- Sivumäärä
- 210
