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Simulated Annealing for VLSI Design
Tallenna

Simulated Annealing for VLSI Design

This monograph represents a summary of our work in the last two years in applying the method of simulated annealing to the solution of problems that arise in the physical design of VLSI circuits.
Painos
Softcover reprint of the original 1st ed. 1988
ISBN
9781461289470
Kieli
englanti
Paino
310 grammaa
Julkaisupäivä
5.10.2011
Sivumäärä
202