Tallenna
Principles of Verifiable RTL Design
Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes.
- Alaotsikko
- A functional coding style supporting verification processes in Verilog
- Kirjailija
- Lionel Bening, Harry D. Foster
- Painos
- Softcover reprint of the original 1st ed. 2000
- ISBN
- 9781475773132
- Kieli
- englanti
- Paino
- 310 grammaa
- Julkaisupäivä
- 12.4.2013
- Kustantaja
- Springer-Verlag New York Inc.
- Sivumäärä
- 253
