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Low Power Interconnect Design
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Low Power Interconnect Design

This book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system.
Kirjailija
Sandeep Saini
Painos
Softcover reprint of the original 1st ed. 2015
ISBN
9781493942947
Kieli
englanti
Paino
310 grammaa
Julkaisupäivä
9.10.2016
Sivumäärä
152