Siirry suoraan sisältöön
Low Power Interconnect Design
Tallenna

Low Power Interconnect Design

Kirjailija:
sidottu, 2015
englanti
This book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system.
Kirjailija
Sandeep Saini
Painos
2012
ISBN
9781461413226
Kieli
englanti
Paino
446 grammaa
Julkaisupäivä
15.6.2015
Sivumäärä
152