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Logic Minimization Algorithms for VLSI Synthesis
Tallenna

Logic Minimization Algorithms for VLSI Synthesis

The fruits of this investigation were surprisingly abundant: it was apparent from an initial implementation of recursive logic minimiza­ tion (ESPRESSO-I) that, if we merged our new results into a two-level minimization program, an important step forward in automatic logic synthesis could result.
Painos
Softcover reprint of the original 1st ed. 1984
ISBN
9781461297840
Kieli
englanti
Paino
310 grammaa
Julkaisupäivä
17.9.2011
Sivumäärä
194