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Logic Minimization Algorithms for VLSI Synthesis
Tallenna

Logic Minimization Algorithms for VLSI Synthesis

The fruits of this investigation were surprisingly abundant: it was apparent from an initial implementation of recursive logic minimiza­ tion (ESPRESSO-I) that, if we merged our new results into a two-level minimization program, an important step forward in automatic logic synthesis could result.
Painos
1984 ed.
ISBN
9780898381641
Kieli
englanti
Paino
446 grammaa
Julkaisupäivä
31.8.1984
Sivumäärä
194