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Logic Synthesis and SOC Prototyping
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Logic Synthesis and SOC Prototyping

Engelsk

This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design.

Undertittel
RTL Design using VHDL
Opplag
2020 ed.
ISBN
9789811513169
Språk
Engelsk
Vekt
310 gram
Utgivelsesdato
30.1.2021
Antall sider
251