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ASIC Design and Synthesis
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ASIC Design and Synthesis

Engelsk
This book describes simple to complex ASIC design practical scenarios using Verilog. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies.
Undertittel
RTL Design Using Verilog
Opplag
2021 ed.
ISBN
9789813346444
Språk
Engelsk
Vekt
310 gram
Utgivelsesdato
8.1.2022
Antall sider
330