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Layout Minimization of CMOS Cells
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Layout Minimization of CMOS Cells

The layout of an integrated circuit (lC) is the process of assigning geometric shape, size and position to the components (transistors and connections) used in its fabrication.
Opplag
Softcover reprint of the original 1st ed. 1992
ISBN
9781461366119
Språk
Engelsk
Vekt
310 gram
Utgivelsesdato
28.9.2012
Antall sider
169