Gå direkte til innholdet
Hierarchical Modeling for VLSI Circuit Testing
Spar

Hierarchical Modeling for VLSI Circuit Testing

To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel.
Opplag
Softcover reprint of the original 1st ed. 1990
ISBN
9781461288190
Språk
Engelsk
Vekt
310 gram
Utgivelsesdato
26.9.2011
Antall sider
160