Spar
Digital Timing Macromodeling for VLSI Design Verification
Forfatter:
heftet, 2012
Engelsk
Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers.
- Forfatter
- Jeong-Taek Kong, David V. Overhauser
- Opplag
- Softcover reprint of the original 1st ed. 1995
- ISBN
- 9781461359821
- Språk
- Engelsk
- Vekt
- 310 gram
- Utgivelsesdato
- 3.10.2012
- Antall sider
- 265
