Spar
A Pipelined Multi-core MIPS Machine
Forfatter:
heftet, 2014
Engelsk
It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.
The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory.
- Undertittel
- Hardware Implementation and Correctness Proof
- Forfatter
- Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul
- Opplag
- 2014 ed.
- ISBN
- 9783319139050
- Språk
- Engelsk
- Vekt
- 310 gram
- Utgivelsesdato
- 1.12.2014
- Antall sider
- 352
