Testing Static Random Access Memories

Embedded memories are one of the fastest growing segments of today's new technology market. According to the 2001 International Technology Roadmap for Semiconductors, embedded memories will continue to dominate the increasing system on chip (SoC) content in the next several years, approaching 94 per cent of the SoC area in about 10 years. Furthermore, the shrinking size of manufacturing structures makes memories more sensitive to defects. Consequently, the memory yield will have a dramatic impact on the overall Defect-per-million level, hence on the overall SoC yield. Meeting a high memory yield requires understanding memory designs, modeling their faulty behaviors, designing adequate tests and diagnosis algorithms as well as efficient self-test and repair schemes. Testing Static Random Access Memories covers testing of one of the important semiconductor memories types; it address testing of static random access memories (SRAMs), both single-port and multi-port. It contributes to the technical acknowledge needed by those involved in memory testing, engineers and researchers. The book begins with outlining the most popular SRAMs architectures. Then, the description of realistic faul