Tallenna
SVA: The Power of Assertions in SystemVerilog
This book is a comprehensive guide to assertion-based verification of hardware designs using System Verilog Assertions (SVA). The book makes SVA usable and accessible for hardware designers, verification engineers, formal verification specialists and EDA tool developers.
- Kirjailija
- Eduard Cerny, Surrendra Dudani, John Havlicek, Dmitry Korchemny
- Painos
- Softcover reprint of the original 2nd ed. 2015
- ISBN
- 9783319331096
- Kieli
- englanti
- Paino
- 310 grammaa
- Julkaisupäivä
- 23.8.2016
- Kustantaja
- Springer International Publishing AG
- Sivumäärä
- 590
