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On-Chip Training NPU - Algorithm, Architecture and SoC Design
Tallenna

On-Chip Training NPU - Algorithm, Architecture and SoC Design

Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design.

Painos
2023 ed.
ISBN
9783031342394
Kieli
englanti
Paino
310 grammaa
Julkaisupäivä
29.7.2024
Sivumäärä
237