Tallenna
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics.
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits).
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits).
- Kirjailija
- Gary D. Hachtel, Fabio Somenzi
- Painos
- Softcover reprint of the original 1st ed. 1996
- ISBN
- 9781475770360
- Kieli
- englanti
- Paino
- 310 grammaa
- Julkaisupäivä
- 18.3.2013
- Kustantaja
- Springer-Verlag New York Inc.
- Sivumäärä
- 564
