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Improving Performance and Reducing Power with Hardware Acceleration - Static Timing Analysis Based Transformations of Combinational Logic in a High Level ASIC Synthesis Flow
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Improving Performance and Reducing Power with Hardware Acceleration - Static Timing Analysis Based Transformations of Combinational Logic in a High Level ASIC Synthesis Flow

pokkari, 2008
englanti
ISBN
9783639106909
Kieli
englanti
Paino
141 grammaa
Julkaisupäivä
30.12.2008
Kustantaja
VDM Verlag
Sivumäärä
96