Improving Code Overlay Performance

Advances in electronics technology and innovative manufacturing processes havedriven the semiconductor industry towards extensive miniaturization & ever greater integrationof chip design. One consequence of this sustained evolution has been the growingrelative cost of accessing off-chip components with external memory being one of the dominantcontributors. In embedded systems and applications, where power consumption andcost are extremely crucial factors, the use of on chip Scratch Pad Memories (SPMs) hasproven to be a good alternative to caches. SPMs are more efficient than on-chip cachesin a wide variety of aspects including energy consumption, power dissipation, speed performance, area, and timing predictability. However, at the same time, they entail explicitsoftware-level management. Specifically, the system performance depends upon overlayscheme for mapping code and data onto the size-limited SPMs. It has been found that forapplications with large code sizes, the overlay overhead cost becomes significant. This workaims to evaluate and implement pre-fetching as a performance improvement technique forSPMs