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Hierarchical Modeling for VLSI Circuit Testing
Tallenna

Hierarchical Modeling for VLSI Circuit Testing

To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel.
Painos
Softcover reprint of the original 1st ed. 1990
ISBN
9781461288190
Kieli
englanti
Paino
310 grammaa
Julkaisupäivä
26.9.2011
Sivumäärä
160