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Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip
Tallenna

Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip

Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.
Painos
1st ed. 2018
ISBN
9783319604015
Kieli
englanti
Paino
446 grammaa
Julkaisupäivä
14.7.2017
Sivumäärä
146