Tallenna
Formal Semantics and Proof Techniques for Optimizing VHDL Models
Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL.
Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.
Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.
- Painos
- Softcover reprint of the original 1st ed. 1999
- ISBN
- 9781461373315
- Kieli
- englanti
- Paino
- 310 grammaa
- Julkaisupäivä
- 26.10.2012
- Kustantaja
- Springer-Verlag New York Inc.
- Sivumäärä
- 158
