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Designing Reliable and Efficient Networks on Chips
Tallenna

Designing Reliable and Efficient Networks on Chips

Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge.

Painos
2009 ed.
ISBN
9781402097560
Kieli
englanti
Paino
446 grammaa
Julkaisupäivä
21.4.2009
Sivumäärä
198