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Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
Tallenna

Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects

The authors provide a historical perspective on the early methods proposed to tackle automatic analog circuit sizing, with emphasis on the methodologies to size and optimize the circuit, and on the methodologies to estimate the circuit’s performance.
Painos
Softcover reprint of the original 1st ed. 2017
ISBN
9783319824857
Kieli
englanti
Paino
310 grammaa
Julkaisupäivä
12.6.2018
Sivumäärä
182