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ASIC Design and Synthesis
Tallenna

ASIC Design and Synthesis

This book describes simple to complex ASIC design practical scenarios using Verilog. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies.
Alaotsikko
RTL Design Using Verilog
Painos
2021 ed.
ISBN
9789813346444
Kieli
englanti
Paino
310 grammaa
Julkaisupäivä
8.1.2022
Sivumäärä
330