Tallenna
A Pipelined Multi-core MIPS Machine
Kirjailija:
nidottu, 2014
englanti
It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.
The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory.
- Alaotsikko
- Hardware Implementation and Correctness Proof
- Kirjailija
- Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul
- Painos
- 2014 ed.
- ISBN
- 9783319139050
- Kieli
- englanti
- Paino
- 310 grammaa
- Julkaisupäivä
- 1.12.2014
- Kustantaja
- Springer International Publishing AG
- Sivumäärä
- 352
