Multiple Constant Multiplication Optimizations for Field Programmable Gate Arrays

This work covers field programmable gate array(FPGA)-specific optimizations of circuits computing the multiplication of avariable by several constants, commonly denoted as multiple constantmultiplication (MCM). These optimizations focus on low resource usage but highperformance. They comprise the use of fast carry-chains in adder-based constantmultiplications including ternary (3-input) adders as well as the integrationof look-up table-based constant multipliers and embedded multipliers to get theoptimal mapping to modern FPGAs. The proposed methods can be used for theefficient implementation of digital filters, discrete transforms and many othercircuits in the domain of digital signal processing, communication and imageprocessing.