Verilog Methods and Practical Analysis on a Running Cycle Project

Academic Paper from the year 2018 in the subject Computer Science - Miscellaneous, grade: 4, University of California, Santa Cruz, course: Verilog Pipeline Cycle, language: English, abstract: This paper is report on Verilog analysis methods and creates a living example on a Verilog project consisting of files that need to be verified and following the pipeline run in a cycle of 4000 times The paper is written in standard IEEE form and is addressed to those with an elementary to medium knowledge of Verilog who are interested following the run procedure and code writing of a project demonstrating Verilog abilities in the required 4000 running cycle. The project made in order to demonstrate how a state machine behaves with fetch, decode and writeback using Verilog. The software used was System Verilog which is a combination of C/C++, Verilog and also Co-Design Automation Superlog language and was run in a home PC. On this manner the level of abstraction was high regardless of the low-cost home PC.