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Layout Minimization of CMOS Cells
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Layout Minimization of CMOS Cells

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The layout of an integrated circuit (lC) is the process of assigning geometric shape, size and position to the components (transistors and connections) used in its fabrication.
Upplaga
Softcover reprint of the original 1st ed. 1992
ISBN
9781461366119
Språk
Engelska
Vikt
310 gram
Utgivningsdatum
2012-09-28
Sidor
169