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A Pipelined Multi-core MIPS Machine
Författare:
häftad, 2014
Engelska
It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.
The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory.
- Undertitel
- Hardware Implementation and Correctness Proof
- Författare
- Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul
- Upplaga
- 2014 ed.
- ISBN
- 9783319139050
- Språk
- Engelska
- Vikt
- 310 gram
- Utgivningsdatum
- 2014-12-01
- Sidor
- 352
