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SystemVerilog for Hardware Description
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SystemVerilog for Hardware Description

Författare:
Engelska
This book introduces the reader to FPGA based design for RTL synthesis. The book builds the story from basic fundamentals of FPGA based designs to advance RTL design and verification concepts using SystemVerilog.
Undertitel
RTL Design and Verification
Författare
Vaibbhav Taraate
Upplaga
2020 ed.
ISBN
9789811544071
Språk
Engelska
Vikt
310 gram
Utgivningsdatum
11.6.2021
Sidor
252