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Principles of Verifiable RTL Design
Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes.
- Undertitel
- A functional coding style supporting verification processes in Verilog
- Författare
- Lionel Bening, Harry D. Foster
- Upplaga
- Softcover reprint of the original 1st ed. 2000
- ISBN
- 9781475773132
- Språk
- Engelska
- Vikt
- 310 gram
- Utgivningsdatum
- 12.4.2013
- Sidor
- 253
