
Logic Synthesis and SOC Prototyping
This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design.
- Undertitel
- RTL Design using VHDL
- Författare
- Vaibbhav Taraate
- Upplaga
- 2020 ed.
- ISBN
- 9789811513169
- Språk
- Engelska
- Vikt
- 310 gram
- Utgivningsdatum
- 2021-01-30
- Sidor
- 251