High Level Synthesis of ASICs under Timing and Synchronization Constraints

Computer-aided synthesis of digital circuits from behavioural level specifications offers an effective means to deal with the increasing complexity of digital hardware systems. This book addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioural level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers. The text addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of an efficient data-path control-unit is the major contribution of this book. Three requirements are important in modelling ASIC designs: concurrency, external synchronization and detailed timing constraints. The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model. The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis.