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Hierarchical Modeling for VLSI Circuit Testing
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Hierarchical Modeling for VLSI Circuit Testing

To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel.
Upplaga
Softcover reprint of the original 1st ed. 1990
ISBN
9781461288190
Språk
Engelska
Vikt
310 gram
Utgivningsdatum
2011-09-26
Sidor
160