
A Practical Guide for SystemVerilog Assertions
Irwan Sie, Director, IC Design, ESS Technology, Inc.
"SystemVerilogAssertions is a new language that can find and isolate bugs early in the design cycle.
- Författare
- Srikanth Vijayaraghavan, Meyyappan Ramanathan
- Upplaga
- 2005 ed.
- ISBN
- 9781489992796
- Språk
- Engelska
- Vikt
- 310 gram
- Utgivningsdatum
- 4.12.2014
- Sidor
- 334