VHDL for Simulation, Synthesis and Formal Proofs of Hardware

The emergence of VHDL, as a standard for hardware description languages helped disseminate the use of such languages among IC designers. The creation of the standard however does not mean that all work has ceased. Research continues in the use of the language and on improvements of the standard. This book presents recent research on four key issues related to the use of VHDL. The first part covers simulation of circuits using VHDL in which timing and switching are central themes. Part 2 looks at the combination of synthesis and VHDL in designing circuits. This includes a case study of chip design using silicon 1076. Advances in the formal verification of VHDL designs are given in Part 3. This relatively new area in the use of VHDL is developing rapidly into an important issue for speeding the design of circuits. The final part considers modelling issues and system level design. The contributions to this volume are based on specially selected papers from EURO-VHDL conferences in 1990 and 1991. These papers have been updated and expanded to give the reader a current state of the art in the use of VHDL in circuit design.