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Digital Timing Macromodeling for VLSI Design Verification
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Digital Timing Macromodeling for VLSI Design Verification

Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers.
Upplaga
Softcover reprint of the original 1st ed. 1995
ISBN
9781461359821
Språk
Engelska
Vikt
310 gram
Utgivningsdatum
2012-10-03
Sidor
265