Tallenna
Direct Transistor-Level Layout for Digital Blocks
The approach described in this book can pack devices much more densely than a typical cell-based layout.
Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.
Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.
- Kirjailija
- Prakash Gopalakrishnan, Rob A. Rutenbar
- Painos
- Softcover reprint of the original 1st ed. 2004
- ISBN
- 9781475779516
- Kieli
- englanti
- Paino
- 310 grammaa
- Julkaisupäivä
- 23.3.2013
- Kustantaja
- Springer-Verlag New York Inc.
- Sivumäärä
- 125
